According to current processes known in the microelectronics industry, the substrate of integrated devices is typically wafers of monocrystalline silicon. In the last few years, as an alternative to wafers consisting of silicon alone, composite wafers, so-called “SOI” (Silicon-on-Insulator) wafers have been proposed, comprising two silicon layers, one of which is thinner than the other, separated by a silicon oxide layer. SOI structures are becoming widely utilized for construction of electronic devices. For example, such structures can be employed to produce semiconductor devices, such as VLSI devices, micro-electro-mechanical systems (MEMS), and optical devices. One method of producing an SOI structure, known by the acronym SIMOX (separation by implanted oxygen) forms a buried oxide layer (BOX) in a semiconductor substrate by implanting oxygen ions into the substrate followed by a high temperature annealing step. The insulating layer provides electrical isolation of devices that are built in the superficial silicon layer.
Considerable attention has recently been paid to SOI wafers, since integrated circuits having a substrate formed from wafers of this type have considerable advantages compared with similar circuits formed on conventional substrates, formed by monocrystalline silicon alone. These advantages include, faster switching speed, greater immunity to noise, smaller loss currents, elimination of parasitic component activation phenomena, reduction of parasitic capacitance, greater resistance to radiation effects, and greater component packing density.
One particular device formed on an SOI is a MOSFET. In order to meet an increasing demand for high-performance portable equipment, demand for SOI-MOSFETs offering the above-mentioned advantages is also expected to increase. As SOI-MOSFETs continue to be reduced in size, one problem that arises concerns the need to maintain high electron/hole mobility in their channels. Unfortunately, increased MOSFET scaling can degrade mobility in very short channels because of the high impurity levels that are employed to suppress short channel effects and because the parasitic resistance becomes more sensitive. Additionally, mobility saturates at very short channel lengths.
MOSFETs may be classified as P-type, in which the channel is doped P-type, or N-type, in which the channel is doped N-type. For a variety of reasons it is often desirable to incorporate both N-MOSFETs and P-MOSFETs in the same circuit. For example, RF analog circuits such as a low noise amplifier using both types of MOSFETS can be fabricated with enhanced performance characteristics such as higher gain and lower current. It is well known that the hole mobility for a P-MOSFET is much higher when it is formed on a silicon substrate with a top surface having a (110) crystal orientation (an “Si(110) surface or layer”) than when it is formed on a silicon substrate with a top surface having a (100) crystal orientation (an “Si(100) surface or layer”). On the other hand, it is also well known that the electron mobility for an N-MOSFET is degraded when it is formed on a Si(110) surface of a substrate in comparison to when it is formed on a Si(100) surface of a substrate. Because of this opposite behavior of electron and hole mobility, it is difficult to integrate an N-MOSFET and a P-MOSFET on the same SOI substrate while maintaining satisfactory performance from both devices.